Embodiments of the present invention relate generally to a logic output buffer, and more particularly, to a low power logic output buffer.
Integrated circuits (ICs) which have logic output buffers are known in the art. A logic output buffer generally receives clock signals CLK and /CLK (i.e., complement of clock CLK) and provides output signals OUT and /OUT (i.e., complement of OUT) which are delayed versions of the clock signals CLK and /CLK. The clock signals CLK and /CLK are typically full swing from a rail supply voltage Vdd1 and ground GND.
An n-type metal oxide semiconductor (NMOS) source follower output buffer can effectively drive a large load, but typically requires a large amount of power supply current and/or a large die size. FIG. 1 shows a conventional NMOS source follower control circuit 100 which is commonly used as a logic output buffer. The conventional NMOS source follower control circuit 100 typically has a relatively high input impedance and a relatively low output impedance. The conventional NMOS source follower control circuit 100 includes input logic gates 1136 and 1139 (NOT gates) which receive clock signals CLK and /CLK, respectively. The conventional NMOS source follower control circuit 100 also includes transistors MN0, MN1, MN2, MN15 and MN16 and biasing resistors R65-R68. Transistors MN0 and MN1 are driven from the outputs of logic gates 1136 and 1139, respectively. The drain of each transistor MN0, MN1 is coupled to the gate of output transistors MN15, MN16, respectively, and to rail voltage Vdd1 dropped through biasing resistors R65, R66, respectively. The sources of both transistors MN0, MN1 are coupled to the drain of bias transistor MN2. The bias transistor MN2 is driven by a bias voltage Vbias and the source of bias transistor MN2 is coupled to ground GND. The drains of both output transistors MN15 and MN16 are coupled to the rail voltage Vdd1 and the sources are respectively coupled to the output pads OUT and /OUT with bias resistors R67, R68 coupled to ground. The bias resistors R67, R68 provide pull-down current for outputs OUT and /OUT which must be strong enough to drive the output load (not shown) during a falling edge of either output OUT or /OUT. The large bias current can be problematic. For example, the rising edge of either output OUT or /OUT is slowed because the source follower transistors MN15, MN16 must drive both the load and the bias resistors R67, R68. This means that transistors MN15, MN16 are constantly dissipating power. Further, the power supply current required for the circuit 100 is relatively large and the circuit 100 generates a relatively large amount of heat.
FIG. 2 shows another conventional NMOS source follower control circuit 200 which is commonly used as a logic output buffer. The conventional NMOS source follower control circuit 200 includes input logic gates 1149 and 1146 (NOT gates) which receive clock signals CLK and /CLK, respectively. The conventional NMOS source follower control circuit 200 also includes transistors MN3, MN4, MN5, MN6, MN7, MN8, MN17 and MN18 and biasing resistors R71-R72. Transistors MN3 and MN4 are driven from the outputs of logic gates 1146 and 1149, respectively. The drain of each transistor MN3, MN4 is coupled to the gate of output transistors MN17, MN18, respectively, and to rail voltage Vdd1 dropped through biasing resistors R71, R72, respectively. The sources of both transistors MN3, MN4 are coupled to the drain of bias transistor MN5. The bias transistor MN5 is driven by a bias voltage Vbias and the source of bias transistor MN5 is coupled to ground GND. The drains of both output transistors MN17 and MN18 are coupled to the rail voltage Vdd1 and the sources are respectively coupled to the output pads OUT and /OUT. The sources of transistors MN17 and MN18 are also coupled to the drains of bias transistors MN8 and MN7, respectively. The gates of the bias transistors MN8 and MN7 are driven by the outputs of logic gates 1146 and 1149, respectively. The sources of both bias transistors MN7, MN8 are coupled to the drain of bias transistor MN6. The bias transistor MN6 is driven by the bias voltage Vbias and the source of bias transistor MN6 is coupled to ground GND. The transistors MN7 and MN8 provide current steering for the source follower transistors MN17, MN18. The bias current is only directed to one of the source follower transistors MN17, MN18 at a time which improves the edge rate and reduces power supply current and heat generation. But, the current steering bias technique requires relatively large current bias or steering transistors MN7 and MN8.
It is desirable to provide a low power logic output buffer that uses a switched bias with a reduced effective load and a smaller footprint die size than conventional logic output buffers.